Radar test set



July 4, 1961 R. J. MocURDY 2,991,469

RADAR TEST SET Filed Q01.. 5l, 1955 5 Sheets-Sheet 1 f1 fz Flcgj l l vw? K1 f2 ff? v MPL. MM Awa, NW. ,4W/24.

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July 4, 1961 v R J, MCCURDY 2,991,469

RADAR TEST SET Filed 0G11. 5l, 1955 5 Shee'S-Sheeb 5 INVENTOR.

.ber/ IHC [ur BY om United `lrStates Patent Filed Oct. 31, 1955, Ser. No. 543,688 Claims. (Cl.`3 43-17 .7)

The present invention relates to an oscillator of improved design, Which is particularly useful for generating circular sweep deflection voltages for cathode ray tube indicaters.

It is a general object of the present invention to provide an improved, inherently stable, resistor-condenser oscillator.` 4

It `is another objectV of the invention to provide an oscillator having substantially no starting transient for producing a wave the lirst cycle of which is of substantially the same shape as subsequent cycles.

It is another object of the invention to provide an improved oscillator which may be started in oscillation in any phase relative to a reference phase.

It is another object of the invention to provide an oscillator which delivers a sinusoidal and cosinusoidal wave simultaneously.

` Yet another object of the invention is to provide an improved test-set which is especially useful for testing radar systems employing so-called type J displays.

A typical embodiment of the invention includes a iirst integrator circuit and a second integrator circuit connected to'integrate the output wave of the iirst integrator circuit. An inverting amplifier receives the output wave of the second integrator circuit and, in turn, supplies its output as the input wave to the irst integrator circuit.

In a preferred form of .the invention, means are provided for clamping the initial level to which the storage means of the integrator circuits are charged. A gate pulse applied to the clamping means effectively removes such means from the circuit, whereby the arrangement described in the preceding paragraph begins to oscillate. The output Wave of the rst integrator circuit means may comprisea sinusoidal wave, whereby the output wave of the second integrator circuit means will comprise a cosinusoidal wave. The levels to which the storage devices of the integration circuits are initially clamped determine the starting phase of the sinusoidal wave and accordingly the starting phase of the cosinusoidal wave.

The invention will be described in greater detail by reference to the following description taken in connection with the accompanying drawing in which:

FIGURE 1 is a functional diagram of a preferred form of the invention;

FIGURE 2 is a graph showing a number of different output waves it is possible to derive from the circuit of FIGURE 1;

FIGURE 3 is a schematic circuit diagram of the arrangement shown in FIGURE l;

IFIGURE 4 is a block circuit diagram of a radar testset according to the present invention;

' FIGURE 5 is a drawing of the waveforms present at various points in the circuits of FIGURES l, 3 and 4; and "FIGURE 6 is a drawing of the display produced inthe test-set of FIGURE 4.

' Similar vreference numerals are applied to similar circuit elements throughout the figures.

Referring'to FIGURE l, the circuit of the invention includes a rst integrator circuit including amplifier 10, resistor R1 and condenser C1; and a second integrator circuit including amplilier 12, resistor R2, and condenser C2.' The output of the second integrator circuit is inverted in a unity-gain, feedback ampliiier 14 and applied over lead 16 into the input circuit of the iirst integrator circuit. .Resistor R3 is a coupling resistor and resistor R4 is in the degenerative feedback loop of the ampliter.

In the circuit of FIGURE l, the output voltage of the rst integrator circuit is e2, the output voltage of the second integration circuit is e3, and the output voltage of amplier 14 is e1. If R1=R2=R and C1=C2=C, the following relationships may be derived:

Combining the Equations l, 2, and 3v to eliminate e2 and e8 gives:

1 el: *amffeldfz Equation 5 is a dierential equation for simple harmonic vibration. Solution of this equation yields the following expression for ,el (see pages 388 and 389 of the 1941 edition of Elements of the Differential and 'Integral Calculus by Granville, Smith, and Longley):

e1=a cos t/RC-l-b sin t/RC (6) The period T of the resultant voltage e1 is: n y T=21rRC (7) The initial phase of e1 can be adjusted to any predetermined value by choosing dierent values of a and b. For example, if a=0 and b=l, the wave 17 shown by the dot-dash line in FIGURE 2 will be obtained; if a=l and b=0, wave 18 shown by the solid line in FIGURE 2 will be obtained; and if a=l and b=1, wave 19 shown by the dashed line in FIGURE 2 will be obtained. Thus, if the initial phase of wave 17 is 0 the second wave 18 leads wave 17v by 90, and the third wave 19 (a=1', b=l) leads wave 17 by 45. The speciiic values of a and b chosen above are merely illustrative of the invention. The general expression for the initial phase 0 of e is:

FIGURE 3 is a schematic circuit diagram of a practical circuit according to the invention. 'Ihe rst integrator comprises a so-called Miller integrator. It includes a pentode 20 having a control grid 22 and an anode 24. Storage capacitor C1 is connected between control grid 22 and anode 24-via cathode follower 26. The cathode follower acts as a coupling device having a relatively high impedance input circuit (the anode circuit of the pentode) and a relatively low impedance output circuit (the grid circuit of the pentode). Dual tiiode 28 is a clamping device which normally conducts and thereby normally maintains control -grid 22 at the potential of .point 30. In the form of the invention illustrated, this potential is maintained at a predetermined value of +87 volts with respect to the cathode of the cathode follower 42 (junction 32) by means of cold cathode gas tube 33. It is to be understood that control grid 22 can be maintained at any other reference level desired by other forms of constant voltage output devices such as, for example, voltage regulator tubes or `even batteries. The value to which this control grid is clamped is the negative value off the a term of equation 6.

The second integrator circuit is similar to thejone described in the preceding paragraph and the same refer'- ence numerals primed are applied to analagous components. In the circuit illustrated, the control grid 22' of pentode is normally clamped to the voltage level of thecathode 34 (the output connection of the r-st integrator) Iby means ofoppositely connected triodes 36. These are connected `across charging resistor R2 and normally effectively short circuit the charging resistor. The output voltage ofthe second'integrator is applied via coupling resistor R3 to control grid 38` of amplifier 40. As in the case ofthe integrator, cathode follower 42 is inserted in the feedback loop for impedance matching purposes. The inverting amplihen is a stable, unity-gain device. The output of amplifier `40. which is available at the cathode connection 32 of cathode follower 42 is fed back via lead 16 and resistor R1 to control grid 22 of the first-integrator.

In operation, clampers 28 and 36 normally conduct. Amplifier 20 conducts and charges storage capacitor C1 to a predetermined level. At the same time, amplifier 20 conducts and charges storage capacitor C2 to another predetermined level. These are determined by the operating potential-s applied to the respective ampliers and the respective levels to which the control grids and storage capacitors-are clamped. When it is desi-red'to make the system oscillate, a negative gate pulse of suflicient amplitude to drive clarnper triodes 28 and 36 to cutoff is applied to terminal 44. It can be seen in a qualitative Way='that when clamper 28 is cut oit, the -bias voltage applied to-control grid 22 of pentode arnpliiierv 20 will become more negative (it will tend to be equal to 300 volts less: the voltage drop across the cathode resistor 46 of cathode follower 42), whereby the plate current drawn by pentode 20 decreasesy and its plate voltage increases. The voltage at the cathode 34 of cathode follower 26 thereby becomesA` more positive. Pentode amplifier 20" now draws more plate current. This in turn causes the anode voltage of the pentode to become more negative,

whereby the voltage available at output terminal 48 becomes more negative.

Mathematical expressionsfor the waves available at terminals 50 (wave e2), 48"(wave e3) and 32` (waveA e1) may be` derived from Equations l, 2, and 6. Referring rst toEquation 6, clamper 28 maintains junction 32 at -87 volts with respect tol the control grid 22 of the first integrator. This is` the a term of the equation. The output terminal 50 ofthe rst integrator is maintained at Olvolts. withl respect to the input circuit to the second integratorvby clamp 36. This is the b term of Equation 6.v Substituting in Equation 6 gives:

e1=-87 cos t/RC (8) Substituting Equation 8 in Equation 1 gives:

e2=-1/RCj`-87 cos t/RC dt e2=87 sin t/RC (9) Substituting Equation '9 in Equation 2 gives:

e3=l/RCf-87 cos t/RC dl e3=87 cos t/RC (10) From the discussion in connection with FIGURE l, it can be seen that the initial phase of oscillation e1 and thereby oscillations e2 and e3 can readily be adjusted by changing thev values of a and b. These in turn are functions of the levels to which the input circuits to the integrators are clamped at T=0 (the time immediately before the gates are applied which cause the circuit to start oscillating). The frequency of oscillations e1, e2, e3 may be controlled by adjustment of R, or C, or both R and C. This is self-evident from Equation 7.

The above-mentioned oscillator is extremely stable. During, the clamping time stability is achieved by using D C. coupling throughout, land by arranging the'clamps tomaintain a'closed feedback loop. By maintaining stabilityv in this way, the clamps may be gated off with substantially no transients resulting. When the clamps are open, voltages e2 and e3 will begin to change as described above and will trace out sine and cosine waves until the clamps are again closed. In a form of the invention to Ibe described in more `detail later, the clamps are opened for a time equahto the period of one oscillation, however, in other form's of the invention -the' clamps may be held open Ifor any length of time desired, either more than or less than the time required for one period.

The circuit ofFIGURE 3'has numerous and important advantages. For one thing, the oscillations may be made to-start yat any predetermined phase. For another,.the circuit is stable and there are substantially no starting transients. This is important when only the first cycle is of interest, .as in the case of a triggered circular sweep. Another advantage is. that when the clamps are closed, the integrating action is stopped and the oscillation is damped out veryl quickly.V Still another advantage is that low frequencies may be obtained without the use of large reactive components. l Y

A practical circuit, designedas shown in FIGURE 3 may include the following elements:

Tubes 28'and 36;. TypeA l2AU7.

Tubes 20, 20 and 40---.. Type 6AU6.V

Tube-33 Typer 5651.

Resistors R1, R2, R3 and R4.l00,000 ohmsl each.-l Condensersl C1 and C2--- 2200 micro-microfaiadseach. Resistor 35 33,000'ohms.

Resistor 46 47,000 ohms.

Referring to FIGURE -4, radar system 60r may beof the type having a centraltime basey from which bothth'e transmitter trigger pulses andthe cathode ray tubesweep potentials are derived. In the case of a radar system employing a typed display, for example,l the central time base may be a sine Wave oscillator the output of which is applied directly to the horizontal .deecting plates of the oscilloscope. The sine waveis also phase shifted andapplied to lthe verticaldeilection plates ofthe oscilloscope. The sine Wave, is also applied to a pulse former such as a phantastron, multivibrator, or the like, which derives from the sine Wave, transmitter triggering pulses. The circuit shownin FIGURE 4 is especially adapted for testing such a system. It displaysV echoes received by the radar system-and. it may be synchronized with the radar system by the radar transmitter pulses or the radar transmitter trigger pulses. It need Vnot be connected 'to the central time base circuits of the-radar system and this isA advantageousv since such connection might be difficult to make and might aifect thepulse repetition-.frequency of the radar system'by unduly loading thesefcircuits.

Still referring to FIGURE 4, detector 62 is connected vialead 64 to a portionof thev radar system through which radio frequency pulsesA pass. For example, lead 6.4-may lead to a probe in the output waveguide of theA radar system. The detector demodulates the pulses andapplies them as triggering signals x to the input circuit of monostablemultivibrator 66. The'output of-thev monostable multivibrator-consists of negative-going gate pulses y suchas shown in FIGURE 5 and these are applied to terminal 44 of circuit 68'- (shown in detail in FIGURES). Voltage e3 available at output terminal 48 is appliedto the vertical deflection plates of ycathode ray' tube indicator 70 and voltage e2 available at terminal 50is applied to the horizontal deflection plates of theindicator. Video information from the radar receiver is-appliedover lead 72 to` the control grid-of the cathoderay tube indicator. The resultant display is as shown in FIGURE 6. Each time a-radar pulsevis-transmitted negative gatery, which is exactly one sine wave period long, is applied to Vter minal 44, and clamps 28 and36 '(FIGURE 3) are opened. One cycle of sine wave is produced at terminal 50` and @Ilsicycl Q cosine Wave is-producedat terminal 48. A

circular trace 74 (FIGURE 6) is produced in response to each transmitter pulse Although not shown in FIGURE 3, resistors R1 and R2 may be made adjustable and ganged and, in like manner, condensers C1 and C2 may also be made adjustable and ganged. This permits the frequency of the sine and cosine waves to be adjusted. Preferably, monostable multivibrator 66 is also made adjustable to permit the duration ofrnegative gate (y) to be adjusted to a value sufficient to permit one complete cycle of oscillator operation. The period to which waves e2 and e3 are adjusted determines the range displayed on the indicator of FIGURE 6. Thus, the lower the frequency, the greater the range and vice-versa.

What is claimed is:

1. A test-set for a radar system of the type including transmitter means for transmitting pulses to reflecting objects and receiver means for detecting pulses reflected from said objects, in combination, means for detecting said transmitted pulses; means responsive to said detected pulses for producing gate pulses having a duration equal to a radar range of interest; resistor-condenser oscillator means responsive to said gate pulses for simultaneously producing a sinusoidal wave and a cosinusoidal Wave, both of which have a period equal to that of the duration of said gate pulses; and cathode ray tube indicator means including means for producing an electron beam, iirst dellecting means for deflecting said beam along one coordinate of the screen of said indicator means, second deecting means for deilecting said beam along another coordinate of the screen of said indicator means, and modulating means for modulating said beam, said sinusoidal signal being applied to said rst deflecting means, said cosinusoidal signal being applied to said second deecting means, and said modulating means being adapted to respond to said detected pulses, and wherein said resistor-condenser oscillator comprises yfirst integrator circuit means; second integrator circuit means connected to receive the output of said rst integrator circuit means for integrating said output; and means for inverting the output of said second integrator circuit means and supplying said output as the input to said rst integrator circuit means, said sinusoidal signal being available at the output of one integrator circuit means, and said cosinusoidal output being available at the output of the other of said integrator circuit means.

2. An oscillator comprising, in combination, first integrator circuit means including a charge storing means; second integrator circuit means connected to receive the output of said rst integrator circuit means for integrating said output, said second integrating means including a charge storing means; means for inverting the output voltage of said second integrator circuit means and supplying said inverted output voltage as the input voltage to said rst integrator circuit means; means coupled to said first and second integrator circuit means for maintaining the charges stored therein at predetermined levels and thereby preventing said oscillator from oscillating; and means for eiectively removing said last-named circuit means from the circuit and thereby permitting said oscillator to oscillate.

3. An oscillator as set forth in claim 2, further including means for adjusting the initial phase of the output voltage of said rst integrator circuit means.

4. An oscillator as set forth in claim 3, wherein said means for adjusting said phase comprises means for adjusting the level to which the charge storing means of said irst integrator circuit is charged before said oscillator begins to oscillate.

5. An oscillator comprising, in combination, a lirst integrator including a rst electron discharge device having at least an anode and control element, and a storage device coupled between said anode and control element; a second integrator including a second electron discharge device having at least an anode and a control element, and a storage device connected between said second device control element and said second device anode, the control element of said second discharge device being connected to receive the output wave of said rst integrator; an inverting amplier including a third electron discharge device having a control element connected to receive the output Wave of said second integrator, and an anode; connection means for coupling the anode of Said third discharge device to the control element of said first discharge device for supplying the output wave of said amplier as the input wave to said first integrator; clamping means coupled to the control electrode of said first discharge device for clamping said first device control electrode to a predetermined voltage level; clamping means coupled to the control electrode of said second discharge device for clamping said second device electrode to-a predetermined voltage level; and means for rendering said clamping means inoperative during intervals it is desired to derive oscillations from said oscillator.

References Cited in the file of this patent UNITED STATES PATENTS 1,924,156 Hart Aug. 29, 1933 2,227,598 Lyman et al. Jan. 7, 1941 2,520,595 Fernsler Aug. 29, 1950 2,605,461 Koehler July 29, 1952 2,621,292 White Dec. 9, 1952 2,776,423 Richardson Jan, 1, 1957 FOREIGN PATENTSV 163,219 Australia Iune 6, 1955 781,374 Great Britain l Aug. 21, 1957 OTHER REFERENCES Corcos et al.: Application of Electronic Differential Analyzer to Eig on Value Problems, pp. 17-24.

Bell et al.: Precision in High-Speed Electronic Differential Analyzers, ppl. 61-79 (pp. 63 and 69 relied on). Both articles are in Cyclone Symposium II, part 2, April 28-May 2, 1952.

Greenwood et al.: Electronic Instruments, Radiation Lab, Series, vol. 2l, 1948, pp. 79-82.

Dorn et al.: Electric Analog Computer, McGraw- Hill Book Co., 1952, pp. 288-294, 343-349 relied on.

An Electronic Voltage Integrator From Review of 30 Scientific Instruments, March 1954 (pp. 275479). 

